The present invention disclosed herein relates to a semiconductor memory device, and more particularly, to a flash memory device capable of reducing charge coupling that occurs between adjacent memory cells coupled to the same row, and a method of programming the same.
A semiconductor memory device is largely classified into a volatile semiconductor memory device and a non-volatile semiconductor memory device. The volatile semiconductor memory device is characterized of fast reading and writing speeds, but has limitations of losing stored content when no power is applied. Contrarily, the non-volatile semiconductor memory device retains the stored content even if no power is applied. Therefore, the non-volatile memory device is used for storing content that must remain regardless of power. The non-volatile memory device includes a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. Since a flash EEPROM (hereinafter, referred to as a flash memory) among non-volatile semiconductor memory devices has the higher degree of integration, compared to a typical EEPROM, it is advantageous to use the flash memory for a high capacity auxiliary memory device.
FIG. 1 shows an array structure including a conventional flash memory device. FIG. 2 shows a vertical sectional view including memory cells 40, 50, and 60 arranged in the same row of FIG. 1.
Referring to FIGS. 1 and 2, a memory cell array 10 may include a plurality of memory blocks including a plurality of bit lines BL1e, BL1o, BL2e, . . . BLmo, which are arranged in parallel. Each memory block may include a plurality of NAND strings corresponding to the respective bit lines BL1e, BL1o, BL2e, . . . BLmo. One memory block in the memory cell array 10 is illustrated as an example in FIG. 1.
Each string may have a string select transistor SST and a ground select transistor GST. A plurality of floating gate transistors M0 to M31 (hereinafter, referred to as memory cells) used for memory cells may be coupled in series between the string select transistor SST and the ground select transistor GST. The memory cells M0 to M31 included in each string may be formed in the same substrate 80. The memory cells M0 to M31 may include adjacent floating gate transistors and shared source-drain terminals in each string. A plurality of word lines WL<0> to WL<31> may intersect each string.
Looking at a structure of adjacent memory cells 40, 50, and 60 coupled to the same row, floating gates 41, 51, and 61, i.e., charge storage elements of the memory cell, may be spaced a predefined distance apart from each other.
A control gate 70 may be formed on the floating gates 41, 51, and 61 of the memory cells 40, 50, and 60. The control gate 70 may also be coupled to the corresponding word line WL<30>.
To program the memory cells, an erase process may be performed to have a predetermined threshold voltage (e.g., −3 V) in the memory cells. Then, a high voltage (e.g., 20 V) may be applied to the word line WL<30> for a predetermined time, which is coupled to a selected memory cell 50. To accurately program the selected memory cell 50, the threshold voltage of the selected memory cell 50 may increase to a higher level, but the threshold voltage of the memory cells 40 and 60 (which are not selected) must stay without change.
When a program voltage is applied to the selected word line WL<30>, the program voltage is commonly supplied to the selected memory cell 50 and unselected memory cells 40 and 60 through the control gate 70. As illustrated in FIG. 2, a parasitic capacitance Cx may be disposed between the adjacent floating gates 41, 51, and 61. Therefore, when the program voltage is applied to the selected word line WL<30>, charge coupling between the selected memory cell 50 and unselected memory cells 40 and 60 occurs due to the parasitic capacitance Cx. Consequently, the threshold voltages of the selected memory cell 50 and unselected memory cells 40 and 60 arise together such that unselected memory cells 40 and 60 adjacent to the selected memory cell 50 are accidentally programmed. At this point, the size of the rising threshold voltage Vth is in proportion to the size (i.e., 2Cx) of the parasitic capacitance Cx between the selected memory 50 and adjacent memory cells 40 and 60.
Due to the change of a threshold voltage in the memory cell, which is caused by charge coupling, an unintended program operation occurs in the unselected memory cell. This is called program disturb. The program disturb in the flash memory device is disclosed in U.S. Pat. No. 5,867,429, entitled “HIGH DENSITY NON-VOLATILE FLASH MEMORY WITHOUT ADVERSE EFFECTS OF ELECTRIC FIELD COUPLING BETWEEN ADJACENT FLOATING GATES.” A method of reprogramming a part of memory cells after performing a program operation, which prevents the change of a threshold voltage in the memory cell due to charge coupling, is disclosed in U.S. Pat. No. 6,807,095, entitled “MULTI-STATE NONVOLATILE MEMORY CAPABLE OF REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENTS.” According to the above method, the extensive threshold voltage distribution due to the charge coupling becomes less wide.
However, an additional program operation is required for adjusting the threshold voltage distribution after performing a general program operation disclosed in U.S. Pat. No. 6,807,095. Consequently, a program time lengthens and controls become complicated. To accurately perform a program process, a new method is required to reduce the change of a threshold voltage, which occurs due to the charge coupling caused by adjacent memory cells arranged in the same row, without an additional program operation or an additional circuit.